1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention is preferably applied to an insulated gate field effect transistor (hereinafter referred to as a power MOSFET) or specifically to a vertical type power MOSFET.
2. Description of Related Art
There have been known a field plate structure and a guard ring structure as structures applied to a peripheral region of a chip (peripheral region of a unit cell) of a semiconductor device. FIG. 36 shows an accumulated channel type planar MOSFET to which the field plate structure is applied as one example of those structures.
As shown in FIG. 36, a p-type layer region 707 which extends to the side distant from a cell region on the surface layer portion of an n.sup.- -type semiconductor layer 702 which is formed on an n.sup.+ -type semiconductor substrate 701 is disposed in the peripheral region of the cell region where a planar MOSFET 700 is formed. This p-type layer region 707 plays a role of preventing a breakdown by forming a PN junction with the n.sup.- -type semiconductor layer 702.
In the peripheral region, there is also provided an electrode 722 which contacts with the p-type layer region 707 via a contact hole formed in an insulating film 718 and which extends to the side distant from the cell region. This electrode 722 is a field plate and its potential is equalized with that of the p-type layer region 707. As a result, because a depletion layer is caused to extend to the periphery of the cell region, a withstand voltage of the device is enhanced.
Further, because a withstand voltage of a semiconductor device is determined by the shape and the like of a region where a PN junction terminates in general, there has been termination technology for weakening an electric field in that region without bias thereof in order to obtain a semiconductor device having a high withstand voltage. As one of such termination technology, there has been proposed a mesa structure as disclosed in Japanese Patent Application Laid-Open No. Hei. 4-239778.
An n-channel type vertical power MOSFET is shown in FIG. 37 as a semiconductor device having the mesa structure. The mesa structure will be explained with reference to FIG. 37.
A semiconductor substrate 820 of the vertical power MOSFET is formed by laminating an n.sup.- -type silicon carbide semiconductor layer 802 and a p-type silicon carbide conductive layer 803 on an n.sup.+ silicon carbide semiconductor substrate 801. A trench 807 is then formed in this substrate, and an oxide film 809 and a gate electrode 810 are formed within the trench 807. A source region 804 is formed further around the trench 807, thus completing a cell region. Then, another trench 805 is formed so as to surround the periphery of the cell region. The trench 805 is formed so that the side face thereof is tapered for example. The mesa structure is what the PN junction composed of the n.sup.- -type silicon carbide semiconductor layer 802 and the p-type silicon carbide conductive layer 803 at the periphery of the cell region is terminated at the side face of the trench 805.
The adoption of such mesa structure allows the withstand voltage of the semiconductor device to be increased. It is noted that, as shown in FIG. 38, there is a case when the mesa structure is arranged such that the side face of a trench 905 is almost vertical relative to the surface of the substrate, not tapered as described above.
However, it has been found that the above-mentioned structures have had the following problems.
Firstly, as for the field plate structure shown in FIG. 36, when silicon carbide is used as a semiconductor material, the critical field strength at which an avalanche breakdown occurs is large by one digit and the concentration of impurity of a drain layer (n.sup.+ -type semiconductor layer 701) can be set high by one digit, as compared to the case of using silicon. Accordingly, it has had advantages that the resistance value of the drain layer can be lowered and the ON resistance can be lowered. However, when the impurity concentration is set high as described above, the extension of the depletion layer toward the side distant from the cell region is suppressed as shown by equipotential lines in FIG. 36 and the concentration of an electric field occurs at the interface of the insulating film 709. Therefore, there has been a problem that, when an avalanche breakdown once occurs at this interface, hot carriers having high energy may be implanted to the insulating film 709, causing a dielectric breakdown of the insulating film 709. This problem occurs in the same manner also when the guard ring structure is adopted.
Meanwhile, there has been a problem in the mesa structure shown in FIG. 37 that the concentration of the electric field occurs at the side part of the trench 805, or more concretely at the connecting part between the interface of the n.sup.- -type silicon carbide semiconductor layer 802 and the p-type silicon carbide conductive layer 803 and the oxide film 809, causing a dielectric breakdown of the oxide film 809 at the part where the electric field is concentrated.
Further, in a case of the mesa structure, there has been another problem that, when the side face of the trench 905 is vertical relative to the surface of the substrate as shown in FIG. 38, the concentration of an electric field is liable to occur also at the corner part of the trench 905 and a dielectric breakdown of an insulating film 909 occurs at this part.